Programmable logic devices (PLDs), such as field-programmable gate arrays (FPGAs), are user-programmable integrated circuits that can be programmed to implement user-defined logic circuits. In a typical FPGA architecture, an array of configurable logic blocks (CLBs) and a programmable interconnect structure are surrounded by a ring of programmable input/output blocks (IOBs). The programmable interconnect structure comprises interconnects and configuration memory cells. Each of the CLBs and the IOBs also includes configuration memory cells. The content of the configuration memory cells determines how the CLBs, the IOBs and the programmable interconnect structure are configured. Additional resources, such as multipliers, block random access memory (BRAM) and microprocessors are also included on an FPGA for use in user-defined circuits. An exemplary FPGA architecture is described by Young in U.S. Pat. No. 5,933,023, entitled “FPGA Architecture Having RAM Blocks with Programmable Word Length and Width and Dedicated Address and Data Lines,” which is incorporated herein by reference.
To realize a user-defined circuit, a configuration bitstream is loaded into the configuration memory cells such that the CLBs and IOBs are configured to implement particular circuit components used in the user-defined circuit. A configuration bitstream is also loaded into the configuration memory cells of the programmable interconnect structure such that the programmable interconnect structure connects the various configured CLBS and IOBs in a desired manner to realize the user-defined circuit.
PLDS are not design specific, but instead afford customers (e.g., circuit designers) the ability to instantiate an almost unlimited number of circuit variations. However, in some cases, it can be desirable to restrict or dedicate a PLD to a particular design, and prevent the use of other designs on that PLD.
For instance, not knowing in advance the purpose to which a given PLD will be dedicated places a heavy burden on the quality and reliability of the PLD because PLD manufacturers must verify the functionality of all advertised features. To avoid disappointing customers, PLD manufacturers discard PLDs that include even relatively minor defects.
Furthermore, PLDs are growing ever larger as manufacturers attempt to satisfy customer demand for devices capable of performing ever more complex tasks. The probability that a particular PLD will contain a defect increases as the die size of the PLD increases. Therefore, process yield decreases with increasing PLD size. PLD defects can be categorized in two general areas: gross defects that render an entire PLD useless or unreliable, and localized defects that affect a relatively small portion of a PLD. It has been found that, for large dice, nearly two thirds of the dice on a given wafer may be discarded because of localized defects. Considering the costs associated with manufacturing large integrated circuits, discarding a large percentage of PLD dice significantly increases the effective cost per unit of the remaining PLDS that are sold.
This yield problem can be mitigated using methods that allow PLDS with limited defects to be sold only to selected customers who will not be disappointed with the specific localized defects in such PLDS. In one such method, PLDs are tested to determine whether they are suitable to implement selected customer designs. As each individual PLD can have different manufacturing defects, a PLD that is found to be unsuitable for one design can, nevertheless, be tested for suitability for additional designs. These test methods typically employ test circuits derived from a customer design and instantiated on the individual PLD of interest to verify resources required for the design. The test circuits thus allow PLD manufacturers to verify the suitability of an individual PLD for a specific design.
A PLD manufacturer may want to prevent customers from using such a specially tested PLD for designs other than the tested design. In addition, if purchasers of such PLDs resell them on the “gray market” without indicating that the PLDs are limited to a specific design, the PLD manufacturer's reputation for quality can be harmed. U.S. patent application Ser. No. 10/199,535 entitled “Methods and Circuits for Dedicating a Programmable Logic Device for Use with Specific Designs,” by Stephen M. Trimberger, which is incorporated herein by reference, discloses a method for applying a digital signature to configuration bitstreams of tested PLDs to restrict the use of the PLDs to the tested designs. The digital signature of a tested design is burned into the tested PLD as an unchangeable value, for example, by programming the digital signature into an antifuse-based one-time-programmable (OTP) memory.
In some cases, it may be desirable to redeploy PLDs that are restricted to accepting a configuration bitstream whose digital signature matches the preset, unchangeable value. For example, a PLD manufacturer may want to repurchase surplus restricted PLDs from one customer and resell those restricted PLDs to a new customer together with a new configuration bitstream for a new design. In another example, a customer that has purchased a PLD dedicated to a particular design may want to use that PLD with an altered or different design. In such instances, in order for the PLD to function with the new configuration bitstream, the digital signature of the new configuration bitstream must match the unchangeable value stored on the PLD. It is, therefore, desirable to force the digital signature of a configuration bitstream to a desired value.